FIG. 1 is a flow chart illustrating a typical prior art EDA tool suite for the behavioral verification of a digital design expressed in a hardware description language (“HDL”). The verification of the design presupposes the existence of a formal design specification used to derive test benches that drive a behavioral simulation of the HDL-expressed digital design. The tool suite computes expected responses and compares these with the outcome of the simulation. When the comparison fails, the designer revises the HDL code that defines the digital design to bring the simulation result into compliance with the formal specification.
The elements of the tool suite cooperate to perform the verification function, and include multiple features not directly related to a behavioral design verification function. The unused features place the price of the tool suite out of reach for many low level digital design projects and small firms.
Most low cost design projects do not begin with a formal design specification. Instead, the designer receives and creates multiple informal specification documents including interface specifications, block diagrams, partial schematic diagrams, waveform diagrams, pseudo code listings, copies of product specifications, and hand written notes, among other items. In the course of the project some or all of these specification documents are subject to revision and even replacement or elimination.
Throughout a project, a design specification, to the extent one exists at all, is informal and exits in the mind of the designer. It is the designer's understanding and interpretation of the myriad documents that serve as a design specification. Because of the pressures of time-to-market and a lack of staff, money, and EDA tool resources, the small project cannot afford the luxury of a formal design specification. Despite these drawbacks, a design is completed and reliable behavioral design validation is rushed or sometimes simply not attempted.
What is needed is a low-cost EDA tool (costing approximately what a word processor costs) that can be run on a standard desktop computer having sufficient memory, a display, a keyboard, and a pointing device.
The low-cost tool should include only the elements necessary for editing a design expressed in a hardware description language, for performing an acceptable behavioral simulation, and for debugging a digital design of moderate size (block) expressed in a hardware description language such as Verilog or VHDL.
The tool should permit every design signal to be selectively controlled and observed.
The tool should provide an easy-to-use interface permitting use of the pointing device to select individual signals and busses for control and observation.
The tool user interface should permit display of state transition graphs highlighted to show regions validated and current state and next edge.
The tool should permit single stepping through validation demonstration sequences.
The tool should be able to display selected waveforms.
The tool should be able to accept user special comments for partitioning the design into testable parts.
The tool should derive demonstration sequences for finite state machine parts and should use automatic selections from a library of standardized demonstration sequence templates for all other parts.
The tool should permit the standardized demonstration sequence templates to be automatically adapted for variations in bus width and the like.
The tool should permit behavioral simulation using demonstration sequences operating at a low level for initial validation and debugging with more complex sequences available for higher assurance validation.